1. Field of the Invention
The present invention relates to a polishing method and a polishing agent used in a semiconductor element manufacturing method, more specifically to a polishing method and a polishing agent used in a step for smoothing the surface of a substrate, especially, smoothing an interlayer insulation film, a step of forming a buried metal wiring portion, a step of forming a buried element separation film, or a step of forming a buried capacitor, or the like.
2. Description of the Related Art
With regard to current ultra-super-large-scale integrated circuits, there is a trend towards reducing the sizes of a transistor and other semiconductor elements and increasing the mounting density. Accordingly, various micro processing techniques are being studied and developed, and the design rule is already set to an order of a sub-half micron.
One of the techniques being developed in order to satisfy the strict requirement of the micro processing is a CMP (chemical mechanical polishing) technique. This technique is essential to the manufacturing process of a semiconductor, in particular, when smoothing an interlayer insulation film, forming a plug, forming a buried metal wiring portion, separation of a buried element, forming a buried capacitor and the like.
FIGS. 1A to 1E are cross sections of an interlayer insulation film, illustrating a step of smoothing the film by use of a CMP technique. First, as shown in FIG. 1A, a silicon oxide film 2 is formed on a silicon substrate 1 a ratio of whose protruding portions occupies 50% of the entire surface, and a first Al wiring portion 3 having a width of 0.3 .mu.m and a height of 0.4 .mu.m is formed on the silicon oxide film 2 by a general lithography method and a general etching method. Next, as shown in FIG. 1B, a silicon oxide film 4 having a thickness of 1.3 .mu.m is formed by a plasma CVD method, and then an abrasion process is carried out so as to smooth the silicon oxide film 4. Various changes in cross-sectional shape of the film are illustrated in FIGS. 1C to FIG. 1E. FIG. 1C shows a cross sectional shape of the film in the case where the abrasion process is completed at an ideal position, whereas FIGS. 1D and 1E each show a cross sectional shape in the case where the abrasion process is excessively carried out.
With the conventional abrasion technique, the abrasion rate changes along with an elapse of time, and therefore it is very difficult to stop the processing at an ideal position as shown in FIG. 1C. Further, in the case where there is a wide space between Al wiring portions, that is, when the silicon oxide film 4 is wide, the center portion of the silicon oxide film has priority to other portions in abrasion, thus causing a so-called dishing.
In the case where the abrasion is excessively carried out as shown in FIG. 1D, the pressure resistance between a second Al wiring portion (not shown) formed on the silicon oxide film 4 and the first Al wiring portion 3 is deteriorated. Further, the abrasion is excessively carried out as shown in FIG. 1E, the first Al wiring portion 3 is in some cases disconnected.
In order to solve the above-described drawbacks, it has been proposed a technique in which an anti-abrasion film 5 made of a material such as Si.sub.3 N.sub.4, having an abrasion rate lower than that of a to-be-polished member (in this case, silicon oxide film) is formed on the wide silicon oxide film 4 as shown in FIG. 2 (Jap. Pat. Appln. KOKAI Publication No. 5-315308). However, this technique entails a problem in which the selection rate (the abrasion rate of the Si.sub.3 N.sub.4 film/the abrasion rate of the silicon oxide film) cannot be set high, thus increasing the number of steps of forming, removing and the like of the anti-abrasion film 5.